Compensating asymmetries of parallel-connected SiC MOSFETs using intelligent gate drivers

• Kompensation von Asymmetrien parallelgeschalteter SiC MOSFETs mittels intelligenter Gate-Treiber

Lüdecke, Christoph; de Doncker, Rik W. (Thesis advisor); Grossner, Ulrike (Thesis advisor)

Aachen : ISEA (2022, 2023)
Book, Dissertation / PhD Thesis

In: Aachener Beiträge des ISEA 166
Page(s)/Article-Nr.: 1 Online-Ressource : Illustrationen, Diagramme

Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2022

Abstract

Compensating Asymmetries of Parallel-Connected SiC MOSFETs Using Intelligent Gate Drivers Due to the increasing demand for climate-friendly mobility, the power density of power electronic systems is becoming increasingly relevant. As a result of their low conduction and switching losses, SiC MOSFETs enable higher power densities, among other things. To increase the current-carrying capacity of the systems, several MOSFETs are connected in parallel. However, asymmetries of the switching cell and component tolerances often prevent an optimal utilization of the parallel-connected power semiconductor devices. In this work, analytical models are presented to describe the switching behavior of parallel-connected SiC MOSFETs for different asymmetries. These models are validated with various simulations and measurements. With statistical evaluations, it is shown that it is possible to compensate geometrical asymmetries of the switching cell by selective placement of the MOSFETs with respect to their device characteristics. In addition, two intelligent gate drivers are presented that allow the switching energies of parallel-connected MOSFETs to be varied. A closed loop control is designed to eliminate the temperature difference of the MOSFETs, enabling the potential of parallel-connected MOSFETs to be better exploited. Thus, the proposed concepts save resources and increase the power density of the system.