Balancing the Switching Losses of Paralleled SiC MOSFETs Using a Stepwise Gate Driver


Christoph Lüdecke, Alireza Aghdaei, Michael Laumen, Rik W. De Doncker, 2021 IEEE Energy Conversion Congress and Exposition (ECCE), 16 November 2021.



This paper presents a multi-stage gate driver based on a switched gate resistor topology for paralleled silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). Commercial gate drivers often slow down switching events with a relatively large gate resistance to compensate for the unbalanced switching losses of MOSFETs connected in parallel. Using the proposed driver topology, it is possible to individually change the gate resistance during the switching event to balance unevenly distributed switching losses of paralleled SiC MOSFETs. Therefore, it enables the equalization of switching losses of multiple MOSFETs even at low gate resistances with fastest switching speeds and thus exploits the full potential of SiC MOSFET technology. The evenly distributed losses prevent a derating of the power converter and allow an increased power density.